Define and specify micro architecture of AI Engine building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements RTL design and debug of complex blocks in Verilog / System Verilog Analyze design metrics and make implementation choices to optimize PPA Work with verification and physical design teams to achieve high quality des

Outstanding written, oral communication, interpersonal, and presentation skills. Ability to multi task and handle multiple simultaneous projects with an unstructured or ambiguous environment. Highly results driven and self motivated with the ability to work as a team member and individually. Understands both user and buyer personas for server and server processor products

Model and analyze hardware and software features to improve products performance, abilities, and cost. Develop tools and algorithms to identify and eliminate performance limiters Design, implement, assess, document and test new features for next gen products Be a developer, leader, and owner of the Architectural Modeling Tool PREFERRED EXPERIENCE Programming skills in C++

Develop/Modify tools and infrastructure used for performance analysis and studies Collaborate closely with multiple teams to deliver solutions and the technology to support them Look for the best out of the box solutions to solve problems or develop our own tools as needed PREFERRED EXPERIENCE Experience building and maintaining web applications is ideal, with a focus on

Support and develop existing AI applications both front and backend Develop, implement, and maintain GPU based clusters, ensuring optimal performance Administer ML/AI platforms Distributed ML services, LLMs, Vector DB and AI inferencing, by managing deployments, resource allocation, monitoring, and security. Collaborate with cross functional teams to address AI infrastruc

Defines, plans and drives projects and program plans based on management and senior technical guidance Scope technical feasibility of new Products by clarifying and analyzing requirements with SW/HW Architects, Technical Leads and E ngineers Develop program schedule by considering various Driver, SW Stack components and HW/FW dependencies, negotiate and create a s taffing

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Engaging with software partner architects and engineers to jointly work on performanceoptimizations, develop benchmarking plans, develop technical collateral (presentations, whitepapers, etc.) to position ML compiler in target market segments, and co develop joint partner demos and proof points. The role may also work withpartners to create SOW for implementations as need

Work with cross functional teams to optimize various parts of the SW stack AI Compiler, AI frameworks, device drivers, and firmware. Work on block & system level performance analysis for VLIW based AI Engine processor architecture. Bring up emerging ML models based on CNN, transformers and characterize performance. Develop and validate VLIW based processor systems on both

We are looking for a Systems Design Engineer to join the System level Test team in San Jose. You will be involved in the silicon life cycle from testing of emulated next generation RTL through to silicon validation. You will have a view of the full system but also will become an expert in certain IP down to the register level. We are looking for someone who can span the r

Defining programming and system interfaces to leverage the performance of AIE accelerators in a portable and scalable way Implementing efficient programming abstractions for ML, signal processing and HPC applications Applying strong software engineering skills to enable the implementation of key application use cases on the next generation architectures Functional/perform

Collaborate with architects, hardware engineers, and firmware engineers to understand the impact of new features on perf & power Analyze design metrics and make implementation choices to optimize PPA Build Power test plan documentation covering all critical design features Develop & execute Power vectors & generate high quality Power data Find CAC optimization opportuniti

Runtime Wrapper Development Design and implement C++ runtime wrappers , APIs, and frameworks for ML model execution. Collaborate with kernel developers to integrate ML operators seamlessly into high level ML frameworks like ONNX . Model Loading and Inference Interface with ONNX / Pytorch runtime engines to deploy the model on CPUs. Develop efficient model loading mechanis

Kernel Development Design and implement highly optimized C++ kernel library for Generative AI models . Collaborate with the research and software teams to integrate these kernels into our existing software stack. Vector Processor Optimization Work closely with hardware engineers to understand the architecture of VLIW vector core units such as MAC , GeMM, and non linear fu

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD